LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
entity frequencies is
    port(clk: in std_logic;
         q: buffer std_logic);
end frequencies;

architecture behave of frequencies is
begin
process(clk)
     variable freq: integer range 0 to 25000000;
begin
    if rising_edge(clk) then
        freq := freq + 1;
        if freq = 25000000 then
            q <= not q;
            freq := 0;
        end if;
    end if;
end process;
end behave;